Technology scaling and the quest for increased energy efficiency have fueled the growth of many-core processors. However with technology scaling, core-to-core variations in maximum frequency (Fmax) and leakage power due to within-die device parameter variations have been increasing.
Many-core processors with on-die network-on-chip (NoC) interconnects are emerging as viable architectures for energy efficient high performance computing (HPC). Aggressive supply voltage scaling of these processors can result in higher energy efficiency. However this efficiency comes at the expense of performance. To compensate for this performance loss, many-core processors can parallelize workloads across more cores. Future trends for energy efficiency expect more small cores integrated on a single die, larger die sizes for increased parallel performance, and lower operating voltages for increased energy efficiency. However, these trends can lead to worsening within-die (WID) variations due to the above-described device scaling.
Current scheduling algorithms are not sophisticated enough to account for within-die variations. This results in operating all cores of a processor at the frequency of the slowest core, resulting in sub-optimal energy efficiencies.